The present invention relates to thin film structures and processes for making same. More particularly, the present invention relates to a thin film transistor wherein each of the source and drain electrodes are formed so as not to overlap any portion of the transistor's channel, thereby reducing or eliminating parasitic capacitance and feed-through voltage.
In a typical bottom-gate transistor structure, a metal gate material is formed on a substrate. The substrate is transparent to ultraviolet (UV) light, while the gate metal is opaque to such light. A dielectric layer is formed over the gate metal, and a layer of active material in which a channel will be formed is deposited over the dielectric layer. The layer of active material may, for example, be intrinsic hydrogenated amorphous silicon (a-Si:H), or other similar material. A nitride passivation layer from which an island is subsequently formed is deposited over the layer of active material. Each of these additional layers is generally also transparent to the UV light. A layer of photoresist is next deposited over the passivation layer. UV light is then directed through the substrate, dielectric layer, active material layer, and passivation layer, where it ultimately exposes the photoresist, except where the UV light is blocked by the gate metal. The photoresist is next developed where it has been exposed to the UV light. The patterned photoresist is used as a mask to etch the nitride passivation layer, in all areas except where exposure of the photoresist was blocked by the gate metal (with the exception of some lateral etching). A nitride passivation island is thereby formed, defined by the gate electrode. Hence, this part of the structure is referred to as "self-aligned".
A contact layer, for example a-Si:H doped to be n+, is then deposited over the various layers. Lithography, or a similar process, is then employed to remove a section of the contact layer lying roughly over the gate metal. Since it is difficult to selectively etch doped a-Si:H over the intrinsic a-Si:H (i.e., remove the former but not the latter), the top passivation island is utilized as the etch-stop to form the source and drain electrodes. The final structure is shown in FIGS. 1(a) and 1(b), in which a thin film transistor (TFT) 10 consists of a substrate 12, gate metal 14 formed on substrate 12, gate dielectric layer 16, active layer 18, top passivation island 20, drain electrode 22 and source electrode 24. However, due to the aforementioned difficulty of selectively controlling the etching between doped a-Si:H and intrinsic a-Si:H, the doped a-Si:H is only doped so far, leaving a certain amount of the doped a-Si:H to overlap passivation island 20, as shown by regions 28 and 30. Hence, this part of the structure is not self-aligned.
While leaving overlaps 28 and 30 alleviates the problem of etching through the doped a-Si:H into the intrinsic a-Si:H, there are several reasons to remove as much of the contact layer overlaying the gate metal as possible. First, the larger the gap 26 between source and drain electrodes, the better the electrical isolation between them. Second, the length L of the channel of the transistor is preset by the transistors performance characteristics, materials, and other parameters. The overlaps 28 and 30 cause the channel to be longer than otherwise necessary, which in turn limits the reduction in size of the overall structure. For example, such length may be 5 or more micrometers (.mu.m) for each of the channel 26, source overlap 28, and drain overlap 30, for a total of 15 or more .mu.m. Very competitive active matrix thin film sensor cells today may be on the order of 50 .mu.m across or smaller including photosensor, electrical connections, etc. Thus, reducing overlap shrinks the length of the transistor, making more room for detector material in the cell and/or more cells in an array of a given size.
Finally, and perhaps most importantly, parasitic capacitance is established between the source/drain electrode material and the gate material where they overlap one another. Parasitic capacitance is illustrated in the schematic diagram of FIG. 2, which is a cell 50 for either display or sensing. Cell 50 is provided with TFT 52, which acts as a switch for addressing the cell. The gate 54 of TFT 52 is connected to gate line 60, and the drain 56 of TFT 52 is connected to data line 62. The source 58 of TFT 52 is connected to either a sensor device (such as a p-i-n photodetector, not shown) or a display device (such as a liquid crystal layer structure, not shown), each generally referred to herein as pixel 66.
The overlaps 28 and 30 shown in FIG. 1(a) effectively results in parasitic capacitance between the source and gate, illustrated by capacitor 64. This parasitic capacitance results in feed-through voltage on the pixel electrode, causing image flicker (inaccuracy in the OFF-to-ON transition) and sticking (inaccuracy in the ON-to-OFF transition) in the case of a display device. In the case of a sensor device, parasitic capacitance results in readout noise. Also, since the overlap may vary from cell to cell across the array (for example, due to variations in the substrate, resolution of the lithography, etc.) the feed-through voltage may similarly vary from cell to cell.
FIG. 3 illustrates a number of the disadvantageous consequences of parasitic capacitance and feed-through voltage. Shown in FIG. 3 is the voltage V.sub.g on gate 54 and the voltage V.sub.d on drain 56 of TFT 52 at times t.sub.1 through t.sub.5. Also shown in FIG. 3 is the actual voltage V.sub.pix at pixel 66, shown as a solid line, and the ideal voltage V.sub.ideal at pixel 66, shown as a dashed line. At time t.sub.1, the voltage on data line 62 is high (typically 5-10 volts). However, the voltage on gate line 60 is low (typically 0 volts). Consequently, the channel of TFT 52 is closed, voltage is not permitted to flow between data line 62 and pixel 66, and for example in the case of a typical back lit liquid crystal display device, the pixel is opaque, or OFF.
At time t.sub.2, the voltage on data line 62 remains high, but the voltage on gate line 60 goes from low to high (typically 10-15 volts). The channel of TFT 52 is consequently opened. This results in application of the voltage from data line 62 to pixel 66, causing pixel 66 to become transparent, or ON in the case of a back lit display. Pixel 66 typically has a certain degree of inherent capacitance, shown as C.sub.pix. Also, due to the architecture of an integrated TFT and pixel structure, there typically is an overlap between the source electrode of the TFT 52 and an electrode of the pixel. This results in a capacitance C.sub.s between the source and pixel, which is in parallel with C.sub.pix. However, as previously mentioned, there is also a capacitance between source 58 and gate 54 due to overlap 30 (FIG. 1(a)). Gate 54 is connected to gate line 60, while source 58 is connected to an electrode of pixel 66. This is represented by the capacitance C.sub.gs, shown in FIG. 2, between gate line 60 and pixel 66. Thus, between time t.sub.2 and time t.sub.3, voltage at pixel 66 is as intended.
At time t.sub.3, the voltage on gate line 60 is switched to low. Charge in the channel of TFT 52 is thereby depleted. However, at this time there is a difference in potential across C.sub.gs, which causes part of the charge stored in C.sub.pix to be redistributed to C.sub.gs, resulting in a voltage drop, .DELTA.V.sub.p, referred to as feed-through voltage. At time t.sub.4, voltage on the data line 62 is low, and the voltage on gate line 60 is switched from low to high. This once again opens the channel of TFT 52. However, since the voltage on data line 62 is low, the capacitances C.sub.pix, C.sub.s, and C.sub.gs are discharged to the line level of data line 62, switching pixel 66 OFF. At time t.sub.5, voltages on both the gate line 60 and the data line 62 are low. However, again there is a difference in potential across C.sub.gs, which causes charge redistribution from C.sub.gs to pixel 66, resulting in another feed-through voltage drop of .DELTA.V.sub.p.
Ideally, the OFF state and ON state voltages are constant, as shown by the dotted line V.sub.ideal. However, the parasitic capacitance contributed by the source electrode overlapping the gate electrode precludes obtaining this ideal response. Rather, at time t.sub.3, when the gate voltage changes from high to low, there is a voltage drop from the value set by data line 62. In the case of a display apparatus, the feed-through voltage results in the aforementioned image "flicker" (brightness variation in OFF-to-ON state). Likewise, at time t.sub.5, the feed-through voltage precludes a clean discharging of C.sub.pix and C.sub.s, resulting in the aforementioned image "sticking" (remaining voltage, and hence transmission of light through the display pixel, from ON-to-OFF state).
Analogously, in the application of cell 50 to sensor applications, the various capacitance and feed-through voltage issues discussed above result in sensor noise. That is, feed-through voltage from gate line 60 through C.sub.gs adds to the voltage being read from the pixel 66, introducing signal error.
The extent of the feed-through voltage is a function of the level of the data line voltage, as expressed by EQU .DELTA.V.sub.p .varies.f(C.sub.pix, C.sub.gs).multidot.V.sub.d
Thus, as V.sub.d varies, for example in greyscale applications, the feed-through voltage varies, which in turn varies the pixel response from what is expected at V.sub.d. This means that grey level control is not uniform, for both display and sensing applications.
Several approaches have been pursued in the art to attempt to address the problems of parasitic capacitance and feed-through voltage. In one approach, ion implantation was used to form the source and drain electrodes in the same layer as the channel. The ions were introduced from the upper surface, using the passivation island as a mask. The ion implantation, however, results in structural damage at the locations of implantation. Annealing was used to eliminate this damage. Laser annealing, as opposed to thermal annealing, was used to reduce hydrogen out-diffusion, which would otherwise destroy the channel conductivity. The laser beam was introduced into the structure from the substrate side, and the gate electrode used as a mask to form the source and drain electrodes. However, the laser beam introduced from the substrate side of the structure is not able to anneal the material closest to the channel, since it is shadowed by the edge of the gate electrode. Thus damaged material remains between the source and channel and the gate and channel.
In another approach, a structure is formed as previously described. A layer of chromium is then deposited over the a-Si:H source/drain electrode layer. It is postulated that this results in the formation of chromium silicide. This material may then be selectively etched without damaging the underlying intrinsic a-Si:H channel layer. Etching continues to below the top surface of the passivation island. However, there are two problems with this approach. First, an overlap between source/drain and gate results, similar to that described immediately above, caused by the differences in width of the gate electrode and passivation island. This overlap precludes complete elimination of the problem of parasitic capacitance. Second, the contact resistance of the chromium suicide is very high. This is true despite efforts to dope the layer for improved conductivity.
In yet another approach, selective etching is proposed by employing negative photoresist (in which the exposed material is caused to be resistant to etching). A structure is fabricated as previously described. Active photoresist is deposited over the a-Si:H source/drain electrode layer. The structure is exposed from below, using the gate electrode as a mask. The structure is etched, removing the unexposed portion overlying the gate electrode. Provided the structure may be etched for a sufficient time (dictating the source/drain electrode layer thickness), lateral etching may be employed to remove the material which would otherwise form an overlap with the gate electrode. However, this approach appears to require a channel thickness above the optimal thickness for the TFT in order to avoid over etching into the channel layer.
Accordingly, there is a need in the art for an improved thin film transistor structure, and process for making same, which eliminates overlap between source and drain electrodes on the one hand and the gate electrode on the other. In an array of such structures, in which the TFTs switch pixels, such a structure would provide significantly improved device performance by eliminating parasitic capacitance and feed-through voltage between the source electrode and pixel. Cell to cell variation in device geometry and performance may also be significantly reduced. Device geometries may also be scaled down.